1. Field of the Invention
This invention is related to the field of electronic circuits and, more particularly, to capturing a register value to another clock domain within an integrated circuit.
2. Description of the Related Art Integrated circuits typically include test circuitry used to allow testing of the integrated circuits at manufacturing time or even in a system with other integrated circuits. For example, the test access port (TAP) defined by the Joint Test Access Group (JTAG) and later refined into Institute of Electrical and Electronics Engineers (IEEE) standard 1149.1 is a popular test circuit. The JTAG TAP typically operates at a relatively low clock frequency (e.g. 10 MHz). However, the other circuitry within the integrated circuit may operate at a significantly higher frequency (e.g. 33 MHz to approximately 1 GHz is possible today, and higher frequencies than 1 GHz are expected in the future). Thus, the JTAG TAP is said to be in a first clock domain and the other circuitry in the integrated circuit is said to be in a second clock domain different than the first.
If the TAP is activated while the integrated circuit is in operation and the test requires capturing values from the integrated circuit into the TAP controller, then the test involves transferring a value from a register in the second clock domain to a register in the first clock domain. Since the clocks are of different frequencies (and/or may have phase differences with respect to each other or no phase relationship at all), the transfer must be synchronized in some fashion. This transfer may be particularly problematic if the value to be transferred is changing at the time the value is being transferred. For example, a register in the first clock domain may be configured to receive a multi-bit register value from the second clock domain one bit at a time. If the multi-bit register value is changing during the synchronization, some bits of the multi-bit value may reflect the value prior to the change, and other bits of the multi-bit value may reflect the value subsequent to the change. Thus, the resulting multi-bit value in the first clock domain may be inaccurate. Even if the multi-bit value is synchronized in parallel, some of the bits may synchronize on one clock of the first clock domain and other bits may synchronize on another clock. Thus, the synchronized value in the first clock domain may not reflect the state of the multi-bit value.
The above problem may be even further exacerbated for registers that are changing frequently (e.g. a counter that increments each period of the second clock domain or periodically each N periods). Values from these registers may be even more likely to be synchronized into the JTAG TAP clock domain as invalid values.
The problems outlined above are in large part solved by an integrated circuit as described herein. The integrated circuit includes an address register, clocked by the clock signal corresponding to the TAP and thus in a first clock domain, used to address a control/status register within the integrated circuit. The address register receives a signal indicating that an address is to be loaded into the address register. A control circuit is coupled to receive the signal and to generate a second signal responsive to the address register being loaded. The control register may generate the second signal after the address register has stabilized for observation in a second clock domain corresponding to the clock signal of the integrated circuit. A shadow register, clocked by the clock signal of the integrated circuit and thus in the second clock domain, is coupled to receive the second signal and to load a value from the control/status register addressed by the address loaded into the address register responsive to the second signal. In this manner, a valid value from the addressed register is synchronized in the second clock domain. The value for the shadow register may subsequently be synchronized into the first clock domain (of the TAP), and subsequently transferred out of the integrated circuit via the test interface.
A similar sequence may be performed for a write from the TAP to a control/status register. More particularly, the control circuit may receive the signal indicating that an address is loaded into the address register and may generate a second signal to select the addressed control/status register in response to the signal (after the address register is stabilized for observation in the second clock domain). Similarly, the control circuit may receive a third signal indicating that the data to be written is loaded into a data register (in the first clock domain) and may generate a fourth signal in response to the third signal (after the data register is stabilized for observation in the second clock domain). In response to the fourth signal, the data may be loaded into the selected control/status register.